1. Field of the Invention
This invention relates to data memories. More particularly this invention relates to data memories in which data words are stored within an array of memory cells arranged in columns and rows.
2. Description of the Prior Art
It is known to provide data memories, such as cache memories, in which data words are stored within memory cells arranged in an array of columns and rows (a memory cell stores the one or more bits that together comprise a data word, e.g. for 32 bit data words the memory cells would each store 32 bits of data). In order to read data from a particular memory cell, an entire row of memory cells is activated so as to place data signals representing the content of all of the memory cells comprising that row onto output lines for each column. A particular data word from within one memory cell is then selected from amongst those output by the entire row.
A desirable feature of memory is that the read access time should be low. A problem in this regard is that it takes a finite time between selecting a row of memory cells so as to place its data signals onto the output lines and the time at which the voltages on the output lines reach readable values. This time is limited by the finite resistance and capacitance of the elements involved. One way of dealing with this problem has been to use amplifiers on the output lines to provide full rail voltage readable values at the amplifier output before the voltage levels on the signal lines from the memory array have in fact reached such levels.
Whilst the use of such amplifiers is successful in reducing memory access times, it introduces a problem of increasing the power consumption of the data memory. Amplifiers typically consume relatively large amounts of power relative to the other circuit elements in the data memory. In the context of an increasing need to reduce power consumption (e.g. to assist in the production of portable battery powered equipment), the power consumption of such amplifiers becomes a problem.